1. Field of the Invention
The present invention relates to electronics, and, in particular, to configuring bondwires in integrated circuit packaging to reduce crosstalk.
2. Description of the Related Art
This section introduces aspects that may help facilitate a better understanding of the invention. Accordingly, the statements of this section are to be read in this light and are not to be understood as admissions about what is prior art or what is not prior art.
When implementing high-frequency SERDES (SERializer-DESerializer) links in low-cost bondwire (a.k.a. bond wire) packages, one major source of degradation is bondwire-to-bondwire crosstalk. Previous approaches to this problem have used spacing between noisy bondwires and critical signal bondwires as a method for minimizing crosstalk. This method is not suitable for certain applications in which die space is limited.
FIGS. 1a and 1b provide plan and perspective views, respectively, of a portion of a conventional packaged electronic component 100. In particular, FIGS. 1a-b show an exemplary set of bondwires 102a-j that connect bonding pads 104 on the package side of the component 100 to corresponding bonding pads 106 on die 108 on the die side of component 100. In this exemplary embodiment, bondwires 102b, 102c, 102h, and 102i carry reference voltages VSS2, VCC2, VSS1, and VCC1, respectively, while bondwires 102a, 102d, 102e, 102f, 102g, and 102j carry signals. Furthermore, the signals SigP and SigN carried by bondwires 102e and 102f, respectively, are analog differential signals that are relatively sensitive to noise, while the signals and reference voltages carried on bondwires 102a-d and 102g-j are relatively noisy.
The problem with component 100 is that noise on the so-called aggressor bondwires 102a-d and 102g-j can couple via crosstalk into the so-called victim bondwires 102e-f, adversely affecting signal-to-noise ratios of the analog signals carried on those victim bondwires and compromising circuit functions that rely on those analog signals.